Formal Verification
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically expl...
| Format: | Book |
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| Language: | English |
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Morgan Kaufmann Publishers
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Internet
This item is not available through BorrowDirect. Please contact your institution’s interlibrary loan office for further assistance.Stanford University
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ISIL:US-CST |
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