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030701s2004 njua b 001 0 eng |
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|a 2003057671
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|a 0471441481 (hbk.)
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|a 9780471441489 (hbk.)
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|a (OCoLC-I)270501246
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|a (OCoLC-M)52575856
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|a TK7885.7
|b .P37 2004
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1 |
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|a Patman̲āpan̲, Ṭi. Ār
|
| 245 |
1 |
0 |
|a Design through Verilog HDL /
|c T.R. Padmanabhan, B. Bala Tripura Sundari
|
| 260 |
|
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|a Piscataway, N.J. :
|b IEEE Press ;
|a Hoboken, N.J. :
|b Wiley-Interscience,
|c c2004
|
| 300 |
|
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|a xii, 455 p. :
|b ill. ;
|c 25 cm
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| 504 |
|
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|a Includes bibliographical references (p. 449-450) and index
|
| 596 |
|
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|a 31
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| 650 |
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0 |
|a Verilog (Computer hardware description language)
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| 700 |
1 |
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|a Bala Tripura Sundari, B
|q (Bandaru)
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|t BKS
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|b 36105122860310
|c TK7885.7 .P37 2004
|d LC
|x STKS-MONO
|y 36105122860310
|p LOANABLE
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